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INTEGRATED CIRCUITS
DATA SHEET
TDA8760 10-bit high-speed analog-to-digital converter
Product specification Supersedes data of April 1994 File under Integrated Circuits, IC02 1996 Sep 12
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
FEATURES * 10-bit resolution * Sampling rate up to 40 MHz * Total Harmonic Distortion (THD): -65 dB at 4.43 MHz full-scale and a 40 MHz clock frequency * High signal-to-noise ratio over a large analog input frequency range (8.8 effective bits at 10 MHz full-scale input at a 40 MHz clock frequency) * +5 V power supplies * Binary or two's complement 3-state TTL outputs * In-range 3-state TTL output * TTL compatible digital inputs * LOW-level AC clock input signal allowed * Power dissipation 850 mW (typical) * Low analog input capacitance (typ. 4.5 pF), no buffer amplifier required * No external sample-and-hold circuit required * Analog Input; single or differential * External amplitude range control * Voltage controlled regulator included. GENERAL DESCRIPTION APPLICATIONS
TDA8760
* High-speed analog-to-digital conversion for - Video signal digitizing - High Definition TV (HDTV) - Digital video broadcasting (satellite and cable) - Transient signal analysis - High energy physics research - Sigma-delta (SD) modulators - Medical imaging - Radar pulse digitizing.
The TDA8760 is a monolithic bipolar 10-bit Analog-to-Digital Converter (ADC) for video or other applications. It converts the analog input signal into 10-bit binary coded digital words at a maximum sampling rate of 40 MHz. All digital inputs and outputs are TTL compatible. However, a sine wave clock input signal is allowed.
1996 Sep 12
2
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
QUICK REFERENCE DATA SYMBOL VCCA VCCD VCCO ICCA ICCD ICCO ILE DLE AILE fclk(max) PARAMETER analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current DC integral linearity error DC differential linearity error AC integral linearity error maximum clock frequency TDA8760K/2 TDA8760K/4 Ptot Tamb total power dissipation operating ambient temperature 20 40 - 0 - - 850 - - - fclk = 4 MHz fclk = 4 MHz fclk = 40 MHz; fi = 4.43 MHz CONDITIONS MIN. 4.75 4.75 4.75 - - - - - - TYP. 5.0 5.0 5.0 95 40 35 1.0 0.6 1.2
TDA8760
MAX. 5.25 5.25 5.25 100 45 40 2.0 1.0 2.0 V V V
UNIT
mA mA mA LSB LSB LSB
MHz MHz mW C
970 +70
ORDERING INFORMATION TYPE NUMBER TDA8760K/2 TDA8760K/4 PACKAGE NAME PLCC44 DESCRIPTION plastic leaded chip carrier; 44 leads VERSION SOT187-2 SAMPLING FREQUENCY (MHz) 20 40
1996 Sep 12
3
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VI VI
BLOCK DIAGRAM
Philips Semiconductors
10-bit high-speed analog-to-digital converter
V refH 15
V refL 14
VCCA1 7
V CCA2 13
V CCA3 17
V CCD1 3
VCCD2 21
CLK 2
CLK 1 24 OGND1 output ground OGND2 output ground OGND3 output ground OGND4 output ground
AMP
TDA8760
10 11 SAMPLE AND HOLD COARSE ADC FINE DAC FINE ADC AMP
30
37
44
42 43
V CCO3 V CCO4 data outputs
27
29 31 32 33 ERROR CORECTION 34 TTL OUTPUTS 35 36 40 41 26 8 9 12 16 4 20
D9 (MSB) D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) IR
analog ground
digital ground
handbook, full pagewidth
4
22 23 28 25 AGND1 AGND2 AGND3 AGND4 DGND1 DGND2 VCCO1 OTC V CCO2 CS
MBD222 - 2
Product specification
TDA8760
Fig.1 Block diagram for SO187 package.
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
PINNING SYMBOL CLK CLK VCCD1 DGND1 n.c. n.c. VCCA1 AGND1 AGND2 VI VI AGND3 VCCA2 VrefL VrefH AGND4 VCCA3 n.c. n.c. DGND2 VCCD2 CS OTC OGND1 VCCO1 IR D9 VCCO2 D8 OGND2 D7 D6 D5 D4 D3 D2 OGND3 n.c. n.c. D1 1996 Sep 12 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 clock input complementary clock input digital supply voltage (+5 V) digital ground not connected not connected analog supply voltage (+5 V) analog ground analog ground analog input voltage complementary analog input voltage analog ground analog supply voltage (+5 V) reference voltage LOW reference voltage HIGH analog ground analog supply voltage (+5 V) not connected not connected digital ground digital supply voltage (+5 V) chip select input (TTL level input; active HIGH) output two's complement output ground output supply voltage (+5 V) in-range output data output, bit 9 (MSB) output supply voltage (+5 V) data output, bit 8 output ground data output, bit 7 data output, bit 6 data output, bit 5 data output, bit 4 data output, bit 3 data output, bit 2 output ground not connected not connected data output, bit 1 5 DESCRIPTION
TDA8760
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
SYMBOL D0 VCCO3 VCCO4 OGND4 PIN 41 42 43 44 data output, bit 0 (LSB) output supply voltage (+5 V) output supply voltage (+5 V) output ground DESCRIPTION
TDA8760
DGND1
n.c.
n.c.
44
43
42
41
VCCA1 AGND1 AGND2
40
6
5
4
3
2
1
D1
handbook, full pagewidth
D0 (LSB)
OGND4
CLK
CLK
VCCO4
VCCD1
VCCO3
7 8 9
39 n.c. 38 n.c. 37 OGND3 36 D2 35 D3 TDA8760 34 D4 33 D5 32 D6 31 D7 30 OGND2 29 D8
V I 10 VI 11
AGND3 12 V CCA2 13 VrefL 14 VrefH 15 AGND4 16 V CCA3 17 21
DGND2 20
CS 22
OTC 23
OGND1 24
VCCO1 25
26
D9 (MSB) 27
n.c. 18
n.c. 19
28
VCCD2
Fig.2 Pin configuration for SOT187-2.
1996 Sep 12
6
VCCO2
IR
MGA928-1
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCCA VCCD VCCO VCC1 VCC2 VCC3 VI VI(p-p) IO Tstg Tamb Tj HANDLING PARAMETER analog supply voltage digital supply voltage output supply voltage supply voltage difference between VCCA and VCCD supply voltage difference between VCCO and VCCD supply voltage difference between VCCA and VCCO input voltage input voltage for differential clock drive (peak-to-peak value) output current storage temperature operating ambient temperature junction temperature referenced to AGND CONDITIONS MIN. -0.3 -0.3 -0.3 -0.5 -0.5 -0.5 0.3 - - -55 0 -
TDA8760
MAX. +7.0 +7.0 +7.0 +0.5 +0.5 0.5 VCCA VCCD 10 +150 +70 +150 V V V V V V V V
UNIT
mA C C C
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth j-a TDA8760K/4 TDA8760K/2 PARAMETER Thermal resistance from junction to ambient in free air 35 K/W 46 K/W THERMAL RESISTANCE
1996 Sep 12
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Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
TDA8760
CHARACTERISTICS VCCA = VCCD = VCCO = 4.75 to 5.25 V; AGND and DGND shorted together; VCCA - VCCD = VCCO - VCCD = VCCA - VCCO = -0.25 to +0.25 V; Tamb = 0 to +70 C; unless otherwise specified. Typical values measured at VCCA = VCCD = VCCO = 5 V; Tamb = 25 C. SYMBOL Supplies VCCA VCCD VCCO ICCA ICCD ICCO Inputs CLK AND CLK (REFERENCED TO DGND); note 1 VIL VIH IIL IIH ZI CI Vclk LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current input impedance input capacitance AC input voltage for switching (Vclk - Vclk) Vclk or Vclk = 0.4 V Vclk or Vclk = 2.0 V Vclk or Vclk = VCCD fclk = 40 MHz fclk = 40 MHz DC level = 1.5 V DC level = 2.5 V 0 2.0 -400 - - - - 0.5 1.5 - - - - - 2 4.5 - - - - - - 0.8 VCCD - 100 300 - - 2.0 5.0 V V mA mA mA k pF V V analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current all outputs LOW 4.75 4.75 4.75 - - - 5.0 5.0 5.0 95 40 35 5.25 5.25 5.25 100 45 40 V V V mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
OTC AND CS (REFERENCED TO DGND); see Table 3 VIL VIH IIL IIH LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current VIL = 0.8 V VIH = 2.0 V 0 2.0 -400 - 0.8 VCCD - 20 V V A A
1996 Sep 12
8
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
SYMBOL PARAMETER CONDITIONS VrefH - VrefL = 1.5 V VrefH - VrefL = 1.5 V fi = 4.43 MHz fi = 4.43 MHz differential mode; VI = VI; output code 511; Table 1 VCCA = 5 V VCCA = 4.75 V VCCA = 5.25 V VIoffset(s) input offset voltage single mode; VI = VIoffset(s); output code 511; Table 2 VCCA = 5 V VCCA = 4.75 V VCCA = 5.25 V 3.6 3.5 3.6 3.7 - - 3.8 3.65 4.0 3.3 3.2 3.3 3.4 - - 3.6 3.45 3.8 - - - - MIN. TYP. - - - -
TDA8760
MAX.
UNIT A A k pF
VI AND VI (REFERENCED TO AGND); see also Tables 1 and 2 IIL IIH ZI CI VIoffset(d) LOW level input current HIGH level input current input impedance input capacitance input offset voltage 7 22 2 4.5
V V V
V V V
Voltage controlled regulator inputs VrefH and VrefL (referenced to AGND); differential input VrefH VrefL VI(p-p) IrefH IrefL reference voltage HIGH reference voltage LOW input voltage amplitude (peak-to-peak value) input current at VrefH input current at VrefL 4.0 2.5 1.4 - - 4.5 3.0 1.5 10 10 VCCA 3.5 1.6 - - V V V A A
Voltage controlled regulator inputs VrefH and VrefL (referenced to AGND); single input VrefH VrefL VI(p-p) IrefH IrefL reference voltage HIGH reference voltage LOW input voltage amplitude (peak-to-peak value) input current at VrefH input current at VrefL 4.0 2.5 1.3 - - 4.4 3.0 1.4 10 10 VCCA 3.5 1.5 - - V V V A A
Outputs (referenced to DGND) DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO DGND) VOL VOH IO LOW level output voltage HIGH level output voltage output current in 3-state mode IO = 2 mA IO = -0.4 mA 0.4 V < VO < VCCO 0 2.4 -20 - - - 0.4 VCCD +20 V V A
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9
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA8760
MAX.
UNIT
Switching characteristics CLOCK FREQUENCY fclk (note 1; see Fig.3) fclk(min) fclk(max) minimum clock frequency maximum clock frequency TDA8760K/4 TDA8760K/2 tCPH tCPL clock pulse width HIGH clock pulse width LOW note 7 40 20 10 8 - - - - - - - - MHz MHz ns ns - - 1 MHz
Analog signal processing in differential input mode; see Table 1; 50% clock duty factor; VI(p-p) = VrefH - VrefL = 1.5 V LINEARITY ILE DLE AILE OFE DC integral linearity error DC differential linearity error AC integral linearity error offset error fclk = 4 MHz fclk = 4 MHz note 3 VCCA = VCCD = VCCO = 5 V; VI = VI; Tamb = 25 C; output code = 511 VCCA = VCCD = VCCO = 5 V; Tamb = 25 C; VrefH - VrefL = 1.5 V -1 dB -3 dB HARMONICS (fclk = 40 MHZ); see Figs 6, 8 and 9 f1 fall fundamental harmonics (full scale) harmonics (full scale); all components second harmonics third harmonics THD total harmonic distortion fi = 4.43 MHz; note 2 without harmonics; fclk = 40 MHz; fi = 4.43 MHz; Tamb = 25 C SIGNAL-TO-NOISE RATIO; notes 4 and 5; see Figs 6, 8 and 9 SNR signal-to-noise ratio 54 56 - dB fi = 4.43 MHz fi = 4.43 MHz - - - -70 -70 -65 -63 -63 -60 dB dB dB - - 0 dB - - - -3 1.0 0.6 1.2 - 2.0 1.0 2.0 +3 LSB LSB LSB LSB
GE
gain error; amplitude spread between devices
-10
-
+10
LSB
BANDWIDTH (fclk = 40 MHZ); note 9 B Analog bandwidth - - 140 220 - - MHz MHz
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Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
SYMBOL PARAMETER CONDITIONS - - - - - - MIN. TYP. - - - - - -
TDA8760
MAX.
UNIT
EFFECTIVE BITS; notes 4 and 5; see Figs 6, 8 and 9 EB effective bits TDA8760K/2 (fclk = 20 MHz) effective bits TDA8760K/4 (fclk = 40 MHz) fi = 4.43 MHz fi = 7.5 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz TWO-TONE Two-tone two-tone intermodulation rejection fclk = 40 MHz; note 8 -65 dB 8.90 8.70 8.80 8.80 8.70 bits bits bits bits bits
BIT ERROR RATE BER bit error rate fclk = 40 MHz; fi = 4.43 MHz; VI = 16 LSB at code 512 - 2 x 10-12 - times/ samples
DIFFERENTIAL GAIN; SEE Fig.5 Gdiff differential gain fclk = 20 MHz; fi = 4.43 MHz fclk = 40 MHz; fi = 4.43 MHz DIFFERENTIAL PHASE diff differential phase fclk = 40 MHz; fi = 4.43 MHz - 0.1 0.2 deg Analog signal processing in single input mode; see Table 2; 50% clock duty factor; VI(p-p) = VrefH - VrefL = 1.4 V LINEARITY ILE DLE AILE DC integral linearity error DC differential linearity error AC integral linearity error fclk = 4 MHz fclk = 4 MHz note 3 -1 dB -3 dB HARMONICS (fclk = 40 MHZ); see Fig.7 f1 fall fundamental harmonics (full scale) harmonics (full scale); all components second harmonics third harmonics THD total harmonic distortion fi = 4.43 MHz; note 2 fi = 4.43 MHz fi = 4.43 MHz - - - -61 -62 -59 - - - dB dB dB - - 0 dB - - - - - 1.0 0.6 1.2 140 220 2.0 1.0 2.0 - - LSB LSB LSB - - 0.5 1.0 - - % %
BANDWIDTH (fclk = 40 MHZ); note 9 B Analog bandwidth MHz MHz
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Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
SYMBOL PARAMETER CONDITIONS MIN. TYP. -
TDA8760
MAX.
UNIT
SIGNAL-TO-NOISE RATIO; notes 4 and 5; see Fig.7 SNR signal-to-noise ratio without harmonics; fclk = 40 MHz; fi = 4.43 MHz; Tamb = 25 C fi = 4.43 MHz fi = 7.5 MHz fi = 4.43 MHz fi = 10 MHz fclk = 40 MHz; note 8 54 56 dB
EFFECTIVE BITS; notes 4 and 5; see Fig.7 EB effective bits TDA8760K/2 (fclk = 20 MHz) effective bits TDA8760K/4 (fclk = 40 MHz) TWO-TONE Two-tone two-tone intermodulation rejection - -60 - dB - - - - 8.70 8.50 8.50 8.20 - - - - bits bits bits bits
BIT ERROR RATE BER bit error rate fclk = 40 MHz; fi = 4.43 MHz; VI = 16 LSB at code 512 - 2 x 10-12 - times/ samples
DIFFERENTIAL GAIN; see Fig.5 Gdiff differential gain fclk = 20 MHz; fi = 4.43 MHz fclk = 40 MHz; fi = 4.43 MHz DIFFERENTIAL PHASE diff tds th td tdZH tdZL tdHZ tdLZ differential phase fclk = 40 MHz; fi = 4.43 MHz - - 8 - - - - - 0.1 - - 12 0.2 deg - - 0.5 1.0 - - % %
Timing (note 6; see Fig.3; CL = 15 pF) sampling delay time output hold time output delay time 2 - 16 ns ns ns
3-state output delay times (see Fig.4) enable HIGH enable LOW disable HIGH disable LOW 12 12 8 16 16 16 12 20 ns ns ns ns
1996 Sep 12
12
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
Notes 1. The circuit has two clock inputs: CLK and CLK. There are three modes of operation:
TDA8760
a) TTL mode 1: CLK input is at TTL level with a threshold voltage of 1.5 V and sampling is taken on the falling edge of the clock input signal. CLK decoupled to DGND via a 100 nF capacitor. b) TTL mode 2: CLK input is at TTL level with threshold voltage of 1.5 V and sampling is taken on the rising edge of the clock input signal. CLK decoupled to DGND via a 100 nF capacitor. c) TTL mode 3: CLK and CLK inputs are at differential TTL levels. d) AC driving modes: When driving the CLK input directly and with any AC signal of minimum 0.5 V (p-p) and with a DC level of 1.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal.It is recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor. 2. THD (total harmonic distortion) is obtained with the addition of the first five harmonics: F a) THD = 20 log --------------------------------------------------------------------------------------------------------------2 2 2 2 2 (2nd) + (3rd) + (4th) + (5th) + (6th) b) F being the fundamental harmonic referenced at 0 dB for a full-scale sine wave input. 3. AC linearity: full-scale differential sine wave (fi = 4.43 MHz; fclk = 40 MHz). 4. Effective bits with differential input and single input are respectively executed with full scale differential input and full-scale single sine wave. 5. Effective bits are obtained via a Fast Fourier Transformer (FFT) treatment taking 8K acquisition points per period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to SNR: SNR = EB x 6.02 + 1.76 dB. 6. Output data acquisition: the output data is available after the maximum delay of td. 7. tCPH of 9 ns (minimum) can be applied at the penalty of 0.5 effective bit drop compared to typical values. 8. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter. 9. The -3 dB (or -1 dB) analog bandwidth is determined by the 3 dB (or 1 dB) reduction in the reconstructed output, the input being a full-scale sine wave.
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Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
Table 1 Output coding with differential inputs (typical values to AGND); VI(p-p) = VrefH - VrefL = 1.5 V BINARY OUTPUTS CODE underflow 0 1 * 511 * 1022 1023 overflow VI(p-p) <3.025 3.025 - - 3.40 - - 3.775 >3.775 VI(p-p) >3.775 3.775 - - 3.40 - - 3.025 <3.025 IR D9 TO D0 0 1 1 * 1 * 1 1 0 0000000000 0000000000 0000000001 ********** 0111111111 ********** 1111111110 1111111111 1111111111
TDA8760
TWO'S COMPLEMENT OUTPUTS D9 TO D0 1000000000 1000000000 1000000001 ********** 1111111111 ********** 0111111110 0111111111 0111111111
Table 2 Output coding with single inputs (typical values to AGND); VI(p-p) = VrefH - VrefL = 1.4 V; VI(p-p) = 3.7 V BINARY OUTPUTS CODE underflow 0 1 * 511 * 1022 1023 overflow VI(p-p) <3.0 3.0 - - 3.7 - - 4.4 >4.4 IR D9 TO D0 0 1 1 * 1 * 1 1 0 0000000000 0000000000 0000000001 ********** 0111111111 ********** 1111111110 1111111111 1111111111 TWO'S COMPLEMENT OUTPUTS D9 TO D0 1000000000 1000000000 1000000001 ********** 1111111111 ********** 0111111110 0111111111 0111111111
Table 3 Mode selection. OTC 1 0 X(1) Note 1. Where: X = don't care. CS 1 1 0 binary; active two's complement; active high impedance D0 TO D9 AND IR
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Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
TDA8760
t CPL t CPH CLK 1.4 V
sample N
sample N + 1
sample N + 2
Vl
t dS DATA D0 to D7 DATA N-2 DATA N-1 td DATA N
t HD 2.4 V DATA N+1
MBD721
1.4 V 0.4 V
Fig.3 Timing diagram.
full pagewidth
V CCD CS 50 %
t dHZ HIGH 90 % output data t dLZ HIGH output data LOW 10 % 50 % t dZL LOW
t dZH
50 %
TEST tdLZ
V CCD 3.3 k
S1 VCCD VCCD GND GND
tdZL tdHZ tdZH
MBD723
TDA8760 15 pF CS CS = 100 kHz.
S1
Fig.4 Timing diagram and test conditions of 3-state output delay time.
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Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
handbook, full pagewidth
TDA8760
digital output f i = 4.43 MHz CODE 1023 V4
Vi f i = 4.43 MHz
(1)
(1) f i = 4.43 MHz
V3
(1) f i = 4.43 MHz
V2
(1) f i = 4.43 MHz
V1
(1)
DC offset voltage CODE 0
MBD722
V0
(1) Full-scale divided-by-5. V n ( 1 to 4 ) - V0 G diff = maximum of ------------------------------------------ x 100% V0
Fig.5 Differential gain measurement conditions.
9.0 effective bits 8.8 f clk = 20 MHz 40 MHz
MGA931 - 2
9.0 effective bits 8.8 f clk = 20 MHz
MBD223 - 1
8.6
8.6
40 MHz
8.4
8.4
8.2
8.2
8.0 0 4 8 12 20 16 f i (MHz)
8.0 0 2 4 6 8 10 f i (MHz)
Fig.6
Typical effective bits under differential input mode as a function of input signal frequency.
Fig.7
Typical effective bits under single input mode as a function of input signal frequency.
1996 Sep 12
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Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
TDA8760
0 amplitude (dB) -20.2
MRC299
-40.4
-60.6
-80.8
-101
-121 0 1.25 2.50 3.75 5.00 6.25 7.50 8.75 f (MHz) Effective bits: 9.1; THD = -65.81 dB; Harmonic levels (dB): 2nd = -75.54; 3rd = -76.29; 4th = -74.90; 5th = -67.50; 6th = -90.87. 10.0
Fig.8 Fast Fourier Transformer (fclk = 20 MHz; fi = 4.43 MHz); for differential input mode.
0 amplitude (dB) -20
MBD220
-40
-60
-80
-100
-120 0 2.5 5 7.5 10 12.5 15 17.5 f (MHz) Effective bits: 8.92; THD = -65.86 dB; Harmonic levels (dB): 2nd = -70.92; 3rd = -68.48; 4th = -75.32; 5th = - 81.40; 6th = -72.69. 20
Fig.9 Fast Fourier Transformer (fclk = 40 MHz; fi = 4.43 MHz); for differential input mode.
1996 Sep 12
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Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
INTERNAL PIN CONFIGURATION
TDA8760
handbook, full pagewidth
VCCA1 V CCA2 VCCA3 7 13 17
V CCD1 V CCD2 3 VCCA 21
CLK 1
CLK 2 VCCD
VI and VI
10 and 11
30 k AGND V CCA DGND V refL V refH 14 15
30 k 1.5 V
25 and 43
VCCO1 / VCCO4
AGND V CCO3 20 k CS and OTC 22 and 23 1.5 V 31 to 36, 40 and 41 data output bit 7 to 0
TDA8760
DGND 8 9 12 16 4 20
30 and 37
OGND2 / OGND3
MGA978
AGND1 AGND2 AGND3 AGND4 analog ground
DGND1 DGND2 digital ground
Fig.10 Description of input and output circuitry.
1996 Sep 12
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Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
APPLICATION INFORMATION
TDA8760
handbook, full pagewidth
100 nF CLK differential analog inputs 5V 100 nF IN 5V 100 nF
(1)
IN
D0 (LSB) D1 100 nF 7 8 IN 9 10 11 IN
4.7 F
4.7 F
6
5
4
3
2
1 44 43 42 41 40
39 38 37 36 35 D2 D3 D4 D5 D6 D7
(2)
(2)
(2)
(2)
100 nF
12 13 14 15
TDA8760
34 33 32 31 30 29
R1
R2 R3
R4
100 nF
(3) (3)
16 17 18 19 20 21 22 23 24 25 26 27 28 5V 100 nF 100 nF 5V
D8
100 nF 3 V 4.5 V
100 nF
D9 (MSB) 100 nF
5V output format select chip select input
MGA979
The analog, digital and output supplies should be separated and decoupled. (1) Differential clock signals can be applied if required. (2) R1 and R2 must be determined in order to obtain a middle voltage of 3.4 V; see Table 1. (3) VrefH and VrefL must be decoupled to AGND.
Fig.11 Application diagram for differential input mode.
1996 Sep 12
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Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
TDA8760
handbook, full pagewidth
100 nF single analog input 100 nF IN CLK 5V 5V 100 nF
(1)
D0 (LSB) D1 100 nF 7 8 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 D2 D3 D4 D5 D6 D7
100 nF
IN
9 10 11
IN
(2) (2)
100 nF
12 13 14 15
TDA8760
34 33 32 31 30 29
R1
R2
100 nF
(3) (3)
16 17 18 19 20 21 22 23 24 25 26 27 28 5V 100 nF 100 nF 5V
D8
100 nF 3 V 4.5 V
100 nF
D9 (MSB) 100 nF
5V output format select chip select input
MGA980
The analog, digital and output supplies should be separated and decoupled. (1) Differential clock signals can be applied if required. (2) R1 and R2 must be determined in order to obtain 3.4 V at the transformer; see Table 1. Adaptation with the single input signal impedance must be taken care of. (3) VrefH and VrefL must be decoupled to AGND.
Fig.12 Application diagram for differential input mode using an input transformer.
1996 Sep 12
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Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
TDA8760
handbook, full pagewidth
100 nF CLK 5V 100 nF 5V 100 nF
single analog input IN
(1)
D0 (LSB) D1 4.7 F 4.7 F 100 nF 7 8 IN 9 10 11 IN 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 D2 D3 D4 D5 D6 D7
(2)
(2)
(2)
(2)
100 nF
12 13 14 15
TDA8760
34 33 32 31 30 29
R1
R2 R3
R4
100 nF
(3) (3)
16 17 18 19 20 21 22 23 24 25 26 27 28 5V 100 nF 100 nF 5V
D8
100 nF 3 V 4.5 V
100 nF
D9 (MSB) 100 nF
5V output format select chip select input
MGA981
The analog, digital and output supplies should be separated and decoupled. (1) Differential clock signals can be applied if required. (2) R1 = R3; R2 = R4. R1, R2, R3 and R4 must be determined in order to obtain a middle voltage of 3.7 V; see Table 2. (3) VrefH and VrefL must be decoupled to AGND.
Fig.13 Application diagram for single input mode.
1996 Sep 12
21
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
PACKAGE OUTLINE PLCC44: plastic leaded chip carrier; 44 leads
TDA8760
SOT187-2
eD y X A ZE
eE
39
29 28
bp
40
b1 wM 44 HE A e A4 A1 (A 3) k 7 e D HD 17 ZD B vMB vM A 6 18 k 1 Lp detail X
1
pin 1 index
E
0
5 scale
10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.05
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07
45 o
0.180 inches 0.020 0.01 0.165
0.630 0.630 0.695 0.695 0.048 0.057 0.021 0.032 0.656 0.656 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.12 0.590 0.590 0.685 0.685 0.042 0.040 0.013 0.026 0.650 0.650
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT187-2 REFERENCES IEC 112E10 JEDEC MO-047AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-25 97-12-16
1996 Sep 12
22
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all PLCC packages. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
TDA8760
Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Sep 12
23
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8760
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATION These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Sep 12
24
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
NOTES
TDA8760
1996 Sep 12
25
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
NOTES
TDA8760
1996 Sep 12
26
Philips Semiconductors
Product specification
10-bit high-speed analog-to-digital converter
NOTES
TDA8760
1996 Sep 12
27
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA51
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/02/pp28
Date of release: 1996 Sep 12
Document order number:
9397 750 01092

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